Enlarge / The PCIe 6. 0 standard’s ability to interoperate with all older versions of the standard is a point of pride for the PCI-SIG. (credit: PCI-SIG)
The PCI Special Interest Group (PCI-SIG) has finalized version six. 0 of the PCI Express standard , the communication bus that lets all the stuff inside your computer communicate. The new version of the spec comes roughly three years after the particular PCI Express 5. 0 spec was finalized, and version 6th. 0 once again doubles typically the bandwidth of a PCIe lane from 32GT/s (8GB/s in total, or 4GB/s in each direction) to 64GT/s (16GB/s, or 8GB/s in each direction). For a full 16-lane PCIe 6. 0 connection, that’s as much as 256GB/s of total bandwidth, compared to the 32GB/s or 64GB/s of now-common PCIe 3. 0 and 4. 0 connections.
Like past PCIe versions, PCIe 6. 0 will “interoperate and maintain backwards compatibility” with all existing PCIe versions, so your PCIe 4. 0 GPU or SSD will continue to work in a PCIe 6. 0 slot and vice-versa. The PCI-SIG bragged about the specification’s longevity in a blog post by PCI-SIG board member Debendra Das Sharma: “An interconnect technology is considered successful if it can sustain three generations of bandwidth improvement spanning a decade. PCIe architecture has far exceeded that mark. ”
To boost its speeds, PCIe 6. 0 uses a new kind of signaling called “Pulse Amplitude Modulation 4” (PAM4), which allows for faster data transfers than the previous Non-Return-To-Zero (NRZ) signaling at the expense of a higher error rate. To compensate, PCIe 6. 0 includes technologies like Forward Error Correction (FEC) to correct errors and Cyclic Redundancy Checking (CRC) to ask for packets to be retransmitted when errors can’t be corrected. The PCI-SIG says that this combination of technologies should catch all errors without adding latency to the connection.
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